(a) Field of the Invention
The present invention relates to a digital to analog converter (DAC). More specifically, the present invention relates to a current-steering DAC for one bit extension irrespective of mismatch between current elements.
(b) Description of the Related Art
As the VLSI technique has greatly developed, element integrity within a chip has been improved to allow a system on a board to be integrated as a system on a chip. Accordingly, as digital signal processing techniques have recently been enhanced, digital signal processing communication systems such as high-definition TVs, digital TVs, CDPs, digital camcorders, beepers, and cell phones have been substantially developed. In particular, the importance of DACs for converting signals processed by digital circuits in the digital communication system into analog signals has been highlighted.
For example, a transmitter of a radio communication system requires a DAC which supports an excellent dynamic characteristic and prevents reduction of an SNR and distortions of signals. Also, it is needed for all the systems to have a very low power consumption characteristic according to the trend of highly integrated circuits.
The DACs are classified as audio DACs and video DACs. The audio DACs use a sigma-delta converter for realizing high resolution of greater than 16 bits, and the video DACs for digital TVs, video conference systems, and medical video signal processing systems use a current-matrix converter for high-speed resolution. The above-described current-steering DACs are mainly used for high-speed and high-resolution applications because of high speed and high operational rates. Also, intermediate- and low-speed DACs with a ladder structure are applied to portable instruments, industrial mechanical controllers, and digital control amplifiers.
In detail, the DACs are categorized as: decoder-based DACs for receiving N digital input signals, generating 2N reference signals by using a decoder, combining the reference signals into predetermined signals which correspond to the inputs, and outputting analog signals; binary weighted array DACs for assigning appropriate weights in the current, voltage, and charge formats to the binary signals, and arranging the weighted binary signals to generate desired analog signals; resistor-capacitor array DACs for using the advantages of the decoder-based DACs and binary weighted array DACs; and thermometer code based DACs. Recently, in order to achieve high-speed and excellent monotonous increase and low glitch energy, transactions which describe the current-steering division DACs or fully thermometer code schemes for dividing data into low data and high data, applying the binary weighted method to the low bits, and applying the thermometer code method to the high bits have been published.
For example, as to the thermometer code, the number ‘1’ is represented to be ‘000001’ in the 6-bit digital signal and is converted to be ‘000001’ in the thermometer code format, the number ‘2’ is represented to be ‘000010’ in the 6-bit digital signal and is converted to be ‘000011’ in the thermometer code format, and the number ‘3’ is represented to be ‘000011’ in the 6-bit digital signal and is converted to be ‘000111’ in the thermometer code format. That is, the thermometer code is increased step by step, and better linearity is obtained by applying an appropriate current to each code to control one code to be changed when the code is increased by one step.
Regarding prior art, U.S. application No. U.S. Pat. No. 6,667,703B1 filed on Aug. 30, 2002 discloses “Matching Calibration for Digital-to-analog Converter” for calibrating mismatch by using an ADC with better resolution than the DAC to be realized in order to overcome the restricted resolution caused by mismatch in the current-steering DAC. The above-noted prior art uses the ADC with resolution higher than that of the DAC to be realized for the purpose of improving the resolution of a plurality of bits, thus substantially increasing additional power consumption and an area for an additional circuit.
As to second prior art, U.S. application No. U.S. Pat. No. 6,703,956B1 filed on Jan. 8, 2003 discloses “Technique for Improved Linearity of High-precision, Low-current Digital-to-analog Converter” for dividing current cells to increase mismatched degrees of current cells which form a current-steering DAC for the purpose of bit extension of the current-steering DAC.
As to third prior art, the transaction of entitled “A 300-MS/s 14-bit Digital-to-Analog Converter in Logic CMOS” IEEE JSSC vol. 38, no. 5, pp. 734–740, May 2003 discloses a method for measuring mismatch of a DAC and trimming current cells in order to overcome the restricted resolution caused by mismatch of elements in the current-steering DAC.
As to fourth prior art, the transaction of entitled “A 1.5-V 14-bit 100-MS/s Self-Calibrated DAC” IEEE JSSC vol. 38, no. 12, pp. 2,051–2,060, December 2003 discloses a method for using the ADC with a resolution higher than that of the DAC to be realized for the purpose of improving the resolution of a plurality of bits, thereby increasing additional power consumption and an area for an additional circuit.
The resolution can be restricted because of element mismatch between current cells in the above-noted current-steering DACs. Further, the matching characteristic between current cells is to be increased by more than twice for extension of an additional one bit, which increases the area occupied by current cell related circuits by four times to thus increase a required area and power consumption and degrade operational performance. In particular, complexity of the decoding block for converting binary code signals into thermometer code signals and thus minimizing glitches generated at an output terminal of the converter depending on the variation of input digital signals is increased to increase the required area and power consumption.